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19-5247; Rev 0; 4/10
18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface
General Description
The MAX11212 is an ultra-low power (< 300FA max active current), high-resolution, serial-output ADC. This device provides the highest resolution per unit power in the industry, and is optimized for applications that require very high dynamic range with low power such as sensors on a 4mA to 20mA industrial control loop. The MAX11212 provides a high-accuracy internal oscillator that requires no external components. When used with the specified data rates, the internal digital filter provides more than 80dB rejection of 50Hz or 60Hz line noise. The MAX11212 provides a simple 2-wire serial interface in the space-saving, 10-pin FMAXM package. The MAX11212 operates over the -40NC to +85NC temperature range. S 18-Bit Full-Scale Resolution S 720nVRMS Noise (MAX11212B) S 3ppm INL S No Missing Codes S Ultra-Low-Power Dissipation Operating-Mode Current Drain < 300A (max) Sleep-Mode Current Drain < 0.1A S 2.7V to 3.6V Analog Supply Voltage Range S 1.7V to 3.6V Digital and I/O Supply Voltage Range S Fully Differential Signal Inputs S Fully Differential Reference Inputs S Internal System Clock 2.4576MHz (MAX11212A) 2.2528MHz (MAX11212B) S External Clock S Serial 2-Wire Interface (Clock Input and Data Output) S On-Demand Offset and Gain Self-Calibration S -40C to +85C Operating Temperature Range S 2kV ESD Protection S Lead(Pb)-Free and RoHS-Compliant MAX Package
Features
MAX11212
Applications
Sensor Measurement (Temperature and Pressure) Portable Instrumentation Battery Applications Weigh Scales
Ordering Information
PART MAX11212AEUB+* MAX11212BEUB+ PIN-PACKAGE 10 FMAX 10 FMAX OUTPUT RATE (sps) 120 13.75
Note: All devices are specified over the -40C to +85C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *Future product--contact factory for availability.
Selector Guide
RESOLUTION (BITS) 24 20 18 16 4-WIRE SPI, 16-PIN QSOP, PROGRAMMABLE GAIN MAX11210 MAX11206 MAX11209 MAX11213 4-WIRE SPI, 16-PIN QSOP MAX11200 MAX11207 MAX11211 MAX11203 2-WIRE SERIAL, 10-PIN MAX MAX11201 (with buffers) MAX11202 (without buffers) MAX11208 MAX11212 MAX11205
MAX is a registered trademark of Maxim Integrated Products, Inc.
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface MAX11212
ABSOLUTE MAXIMUM RATINGS
Any Pin to GND ....................................................-0.3V to +3.9V AVDD to GND.......................................................-0.3V to +3.9V DVDD to GND ......................................................-0.3V to +3.9V Analog Inputs (AINP, AINN, REFP, REFN) to GND ............................................. -0.3V to (VAVDD + 0.3V) Digital Inputs and Digital Outputs to GND ............................................. -0.3V to (VDVDD + 0.3V) ESDHB (AVDD, AINP, AINN, REFP, REFN, DVDD, CLK, SCLK, RDY/DOUT, GND) ........................................... Q2kV (Note 1) Continuous Power Dissipation (TA = +70NC) 10-Pin FMAX (derate 5.6mW/NC above +70NC) ..........444mW Operating Temperature Range .......................... -40NC to +85NC Junction Temperature .....................................................+150NC Storage Temperature Range............................ -55NC to +150NC Lead Temperature (soldering, 10s) ................................+300NC Soldering Temperature (reflow) ......................................+260NC
Note 1: Human Body Model to specification MIL-STD-883 Method 3015.7.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = +3.6V, VDVDD = +1.8V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ADC PERFORMANCE Noise-Free Resolution Thermal Noise (Notes 2, 3) Integral Nonlinearity Zero Error Zero Drift Full-Scale Error Full-Scale Error Drift Power-Supply Rejection ANALOG INPUTS/REFERENCE INPUTS DC rejection Common-Mode Rejection Normal-Mode 50Hz Rejection Normal-Mode 60Hz Rejection Common-Mode Voltage Range Low input voltage Absolute Input Voltage High input voltage DC Input Leakage AIN Dynamic Input Current REF Dynamic Input Current AIN Input Capacitance Sleep mode (Note 2) CMR NMR50 NMR60 50Hz/60Hz rejection MAX11212A 50Hz/60Hz rejection MAX11212B MAX11212B (Note 6) MAX11212B (Note 6) 90 90 144 65 73 GND GND 30mV VAVDD + 30mV 1 5 7.5 10 80.5 87 VAVDD dB dB V 123 dB AVDD DC rejection DVDD DC rejection 70 90 After calibration, VREFP - VREFN = 2.5V (Note 5) -35 NFR VN INL VOFF (Notes 2, 3) MAX11212A MAX11212B (Note 4) After calibration, VREFP - VREFN = 2.5V -10 -20 1 50 3 0.05 80 100 +35 18 2.1 0.72 +10 +20 Bits FVRMS ppmFSR ppmFSR nV/NC ppmFSR ppmFSR/NC dB
V
FA FA FA pF
2
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18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.6V, VDVDD = +1.8V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.) PARAMETER REF Input Capacitance AIN Voltage Range REF Voltage Range Input Sampling Rate REF Sampling Rate LOGIC INPUTS (SCLK, CLK) Input Current Input Low Voltage Input High Voltage Input Hysteresis External Clock LOGIC OUTPUTS (RDY/DOUT) Output Low Level Output High Level Floating State Leakage Current Floating State Output Capacitance POWER REQUIREMENTS Analog Supply Voltage Digital Supply Voltage Total Operating Current DVDD Operating Current AVDD Operating Current AVDD Sleep Current DVDD Sleep Current 2-WIRE SERIAL-INTERFACE TIMING CHARACTERISITCS SCLK Frequency SCLK Pulse Width Low SCLK Pulse Width High SCLK Rising Edge to Data Valid Transition Time fSCLK t1 t2 t3 60/40 duty cycle 5MHz clock 40/60 duty cycle 5MHz clock 80 80 40 5 MHz ns ns ns AVDD DVDD AVDD + DVDD 2.7 1.7 230 45 185 0.4 0.35 3.6 3.6 300 60 245 2 2 V V FA FA FA FA FA VOL VOH IOL = 1mA; also tested for VDVDD = 3.6V IOH = 1mA; also tested for VDVDD = 3.6V Output leakage current 0.9 x VDVDD 10 9 0.4 V V FA pF VIL VIH VHYS MAX11212A MAX11212B 0.7 x VDVDD 200 2.4576 2.2528 Input leakage current 1 0.3 x VDVDD FA V V mV MHz fS MAX11212A MAX11212B MAX11212A MAX11212B 246 225 246 225 VAINP - VAINN -VREF SYMBOL CONDITIONS MIN TYP 15 +VREF VAVDD MAX UNITS pF V V kHz kHz
MAX11212
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18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface MAX11212
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.6V, VDVDD = +1.8V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.) PARAMETER SCLK Rising Edge Data Hold Time RDY/DOUT Fall to SCLK Rising Edge Next Data Update Time; No Read Allowed Data Conversion Time Data Ready Time After Calibration Starts (CAL + CNV) SCLK High After RDY/DOUT Goes Low to Activate Sleep Mode Time From RDY/DOUT Low to SCLK High for Sleep Mode Activation Data Ready Time After Wake-Up from Sleep Mode Data Ready Time After Calibration from Sleep Mode Wake-Up (CAL + CNV) Note Note Note Note 2: 3: 4: 5: SYMBOL t4 t5 t6 t7 t8 t9 t10 t11 t12 MAX11212A MAX11212B MAX11212A MAX11212B MAX11212A MAX11212B MAX11212A MAX11212B MAX11212A MAX11212B MAX11212A MAX11212B MAX11212A MAX11212B 0 0 0 0 8.6 73 208.4 256.2 CONDITIONS Allows for positive edge data read MIN 3 0 155 169 8.6 73 208.3 256.1 8.6 73 8.6 73 TYP MAX UNITS ns ns Fs ms ms ms
ms
ms
ms
These specifications are not fully tested and are guaranteed by design and/or characterization. VAINP = VAINN. ppmFSR is parts per million of full-scale range. Positive full-scale error includes zero-scale errors.
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18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface
Typical Operating Characteristics
(VAVDD = 3.6V, VDVDD = 1.8V, VREFP - VREFN = VAVDD; internal clock; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
ANALOG ACTIVE CURRENT vs. AVDD VOLTAGE (MAX11212A)
MAX11212 toc01
MAX11212
ANALOG ACTIVE CURRENT vs. AVDD VOLTAGE (MAX11212B)
VDVDD = 1.8V 220 200 CURRENT (A) 180 160 140 120 100 0.2 TA = +85C TA = +25C TA = -45C
MAX11212 toc02
ANALOG SLEEP CURRENT vs. AVDD VOLTAGE (MAX11212A/MAX11212B)
VDVDD = 1.8V 0.8 CURRENT (A) 0.6 0.4 TA = +85C TA = -45C
MAX11212 toc03
240 VDVDD = 1.8V 220 200 CURRENT (A) 180 160 140 120 100 2.70 2.85 3.00 3.15 3.30 3.45 TA = +85C TA = +25C TA = -45C
240
1.0
TA = +25C 0 2.70 2.85 3.00 3.15 3.30 3.45 3.60
3.60
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 AVDD VOLTAGE (V)
AVDD VOLTAGE (V)
AVDD VOLTAGE (V)
ACTIVE SUPPLY CURRENT vs. TEMPERATURE (MAX11212A)
MAX11212 toc04
ACTIVE SUPPLY CURRENT vs. TEMPERATURE (MAX11212B)
MAX11212 toc05
SLEEP CURRENT vs. TEMPERATURE (MAX11212A/MAX11212B)
VAVDD = 3.6V VDVDD = 1.8V
MAX11212 toc06
300 250 200 150 100 VDVDD = 1.8V 50 0 -45 -25 -5 15 35 55 75
300 250 TOTAL CURRENT (A) 200 VAVDD = 3.6V 150 100 50 0 VDVDD = 1.8V
1.0 0.8 CURRENT (A) 0.6 0.4 0.2 0 VDVDD TOTAL
TOTAL VAVDD = 3.6V
CURRENT (A)
VAVDD
95
-45
-25
-5
15
35
55
75
95
-45
-25
-5
15
35
55
75
95
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
DIGITAL ACTIVE CURRENT vs. DVDD VOLTAGE
MAX11212 toc07
DIGITAL SLEEP CURRENT vs. DVDD VOLTAGE (MAX11212A/MAX11212B)
MAX11212 toc08
INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE
VDVDD = 1.8V VAVDD = 3.0V
MAX11212 toc09
130 120 110
CURRENT (A)
VAVDD = 3.6V TA = +85C, +25C, -45C
3.0 VAVDD = 3.6V 2.5 2.0 1.5 1.0 TA = +85C 0.5 0 TA = -45C TA = +25C
2.6 2.5 FREQUENCY (MHz) 2.4 2.3 2.2 2.1 2.0 MAX11212B MAX11212A
90 80 70 60 50 40 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 DVDD VOLTAGE (V) MAX11212B
CURRENT (A)
100
MAX11212A
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 DVDD VOLTAGE (V)
-45
-25
-5
15
35
55
75
95
TEMPERATURE (C)
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18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface MAX11212
Typical Operating Characteristics (continued)
(VAVDD = 3.6V, VDVDD = 1.8V, VREFP - VREFN = VAVDD; internal clock; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
INTERNAL OSCILLATOR FREQUENCY vs. AVDD VOLTAGE
MAX11212 toc10
OFFSET ERROR vs. VREF (MAX11212A/MAX11212B)
MAX11212 toc11
OFFSET ERROR vs. TEMPERATURE (MAX11212A/MAX11212B)
CALIBRATED AT +25C
MAX11212 toc12
2.6 VDVDD = 1.8V 2.5 FREQUENCY (MHz) 2.4 2.3 2.2 2.1 2.70 2.85 3.00 3.15 3.30 3.45 MAX11212A
2.0 1.5 OFFSET ERROR (ppmFSR) 1.0 0.5 0 -0.5 -1.0
VREF = VREFP - VREFN TA = +25C
2.5 2.0 1.5 1.0 0.5 0
MAX11212B
TA = +85C
TA = -45C
3.60
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OFFSET ERROR (ppmFSR)
-45
-25
-5
15
35
55
75
95
AVDD VOLTAGE (V)
VREF VOLTAGE (V)
TEMPERATURE (C)
INTEGRAL NONLINEARITY vs. INPUT VOLTAGE (MAX11212A/MAX11212B)
MAX11212 toc13
FULL-SCALE ERROR vs. TEMPERATURE (MAX11212A/MAX11212B)
MAX11212 toc14
PSRR vs. FREQUENCY (MAX11212A)
-20 -40 PSRR (dB) -60 -80 -100 VAVDD VDVDD
MAX11212 toc15
NORMALIZED FULL-SCALE ERROR (ppmFSR)
10 8 6 4 INL (ppmFSR) 2 0 -2 -4 -6 -8 -10
VAVDD = 3.0V VDVDD = 1.8V VREF = 2.5V VIN(CM) = 1.5V TA = +85C TA = +25C
10 8 6 4 2 0 -2 -4 -6 -8 -10 -45 -25 -5 15 35 +FS ERROR
VREF = 2.5V
0
TA = -45C
-FS ERROR
-120 -140
-2.5 -2.0 -1.5 -1.0 -0.5 0
0.5 1.0 1.5 2.0 2.5
55
75
1
10
100
1k
10k
100k
INPUT VOLTAGE (V)
TEMPERATURE (C)
FREQUENCY (Hz)
PSRR vs. FREQUENCY (MAX11212B)
MAX11212 toc16
CMRR vs. FREQUENCY (MAX11212A/MAX11212B)
MAX11212 toc17
NORMAL-MODE FREQUENCY RESPONSE (MAX11212A)
-20 -40 GAIN (dB) -60 -80 -100 -120 -140
MAX11212 toc18
0 -20 -40 -60 -80 -100 -120 -140 1 10 100 1k 10k VDVDD VAVDD
0 -20 -40 CMRR (dB) -60 -80 -100 -120 -140 MAX11212A
0
PSRR (dB)
MAX11212B 1 10 100 1k 10k 100k
100k
1
10
100
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
6
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18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface
Typical Operating Characteristics (continued)
(VAVDD = 3.6V, VDVDD = 1.8V, VREFP - VREFN = VAVDD; internal clock; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
NORMAL-MODE FREQUENCY RESPONSE (MAX11212B)
MAX11212 toc19
MAX11212
NORMAL-MODE REJECTION OF 50Hz TO 60Hz (MAX11212B)
-20 -40 GAIN (dB) -60 -80 -100 -120 -140
MAX11212 toc20
0 -20 -40 GAIN (dB) -60 -80 -100 -120 -140 1 10 100
0
1k
40
45
50
55
60
65
70
FREQUENCY (Hz)
FREQUENCY (Hz)
Functional Diagram
AVDD DVDD GND AINP AINN REFP REFN
TIMING
CLOCK GENERATOR
CLK
3RD-ORDER DELTA-SIGMA MODULATOR
DIGITAL FILTER (SINC4)
DIGITAL LOGIC AND SERIALINTERFACE CONTROLLER
SCLK
RDY/DOUT
MAX11212
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18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface MAX11212
Pin Configuration
TOP VIEW +
GND 1 REFP REFN AINN AINP 2 3 4 5 10 CLK 9 8 7 6 SCLK RDY/DOUT DVDD AVDD
MAX11212
MAX
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 NAME GND REFP REFN AINN AINP AVDD DVDD FUNCTION Ground. Ground reference for analog and digital circuitry. Differential Reference Positive Input. REFP must be more positive than REFN. Connect REFP to a voltage between AVDD and GND. Differential Reference Negative Input. REFN must be more negative than REFP. Connect REFN to a voltage between AVDD and GND. Negative Fully Differential Analog Input Positive Fully Differential Analog Input Analog Supply Voltage. Connect a supply voltage between +2.7V to +3.6V with respect to GND. Digital Supply Voltage. Connect a digital supply voltage between +1.7V to +3.6V with respect to GND.
Data-Ready Output/Serial-Data Output. This output serves a dual function. In addition to the serial-data output RDY/DOUT function, the RDY/DOUT also indicates that the data is ready when the RDY is logic-low. RDY/DOUT changes on the falling edge of SCLK. SCLK CLK Serial-Clock Input. Apply an external serial clock to SCLK. External Clock Signal Input. The internal clock shuts down when CLK is driven by an external clock. Use a 2.4576MHz oscillator (MAX11212A) or a 2.2528MHz oscillator (MAX11212B).
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18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface
Detailed Description
The MAX11212 is an ultra-low-power (< 240FA active), high-resolution, low-speed, serial-output ADC. This device provides the highest resolution per unit power in the industry, and is optimized for applications that require very high dynamic range with low power such as sensors on a 4mA to 20mA industrial control loop. The MAX11212 provides a high-accuracy internal oscillator, which requires no external components. When used with the specified data rates, the internal digital filter provides more than 80dB rejection of 50Hz or 60Hz line noise. The MAX11212 provides a simple, system-friendly, 2-wire serial interface in the space-saving, 10-pin FMAX package. The MAX11212 utilizes power-on reset (POR) supplymonitoring circuitry on both the digital supply (DVDD) and the analog supply (AVDD). The POR circuitry ensures proper device default conditions after either a digital or analog power-sequencing event. The MAX11212 performs a self-calibration operation as part of the startup initialization sequence whenever a digital POR is triggered. It is important to have a stable reference voltage available at the REFP and REFN pins to ensure an accurate calibration cycle. If the reference voltage is not stable during a POR event, the part should be calibrated once the reference has stabilized. The part can be programmed for calibration by using 26 SCLKs as shown in Figure 3. The digital POR trigger threshold is approximately 1.2V and has 100mV of hysteresis. The analog POR trigger threshold is approximately 1.25V and has 100mV of hysteresis. Both POR circuits have lowpass filters that prevent high-frequency supply glitches from triggering the POR. The analog supply (AVDD) and the digital supply (DVDD) pins should be bypassed using 0.1FF capacitors placed as close as possible to the package pin. The MAX11212 accepts two analog inputs (AINP and AINN). The modulator input range is bipolar (-VREF to +VREF). The MAX11212 incorporates a highly stable internal oscillator that provides the system clock. The system clock runs the internal state machine and is trimmed to
MAX11212
2.4576MHz (MAX11212A) or 2.2528MHz (MAX11212B). The internal oscillator clock is divided down to run the digital and analog timing. The MAX11212 provides differential inputs REFP and REFN for an external reference voltage. Connect the external reference directly across REFP and REFN to obtain the differential reference voltage. The commonmode voltage range for VREFP and VREFN is between 0 and VAVDD. The differential voltage range for REFP and REFN is 1V to VAVDD. The MAX11212 contains an on-chip, digital lowpass filter that processes the 1-bit data stream from the modulator using a SINC4 (sinx/x)4 response. When the device is operating in single-cycle conversion mode, the filter is reset at the end of the conversion cycle. When operating in continuous conversion latent mode, the filter is not reset. The SINC4 filter has a -3dB frequency equal to 24% of the data rate. The MAX11212 communicates through a 2-wire serial interface with a clock input and data output. The output rate is predetermined based on the package option (MAX11212A at 120sps and MAX11212B at 13.75sps). 2-Wire Interface The MAX11212 is compatible with the 2-wire interface and uses SCLK and RDY/DOUT for serial communications. In this mode, all controls are implemented by timing the high or low phase of the SCLK. The 2-wire serial interface only allows for data to be read out through the RDY/DOUT output. Supply the serial clock to SCLK to shift the conversion data out. The RDY/DOUT is used to signal data ready, as well as reading the data out when SCLK pulses are applied. RDY/DOUT is high by default. The MAX11212 pulls RDY/DOUT low when data is available at the end of conversion, and stays low until clock pulses are applied at SCLK input; on applying the clock pulses at SCLK, the RDY/DOUT outputs the conversion data on every SCLK positive edge. To monitor data availability, pull RDY/DOUT high after reading the 18 bits of data by supplying a 25th SCLK pulse. The different operational modes using this 2-wire interface are described in the following sections.
Reference
Digital Filter
Power-On Reset (POR)
Serial-Digital Interface
Analog Inputs
Internal Oscillator
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18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface MAX11212
Data Read Following Every Conversion The MAX11212 indicates conversion data availability as well as allows the retrieval of data through the RDY/DOUT output. The RDY/DOUT output idles at the value of the last bit read unless a 25th SCLK pulse is provided, causing RDY/DOUT to idle high. RDY/DOUT is pulled low when the conversion data is available. Figure 1 shows the timing diagram for the data read. Once a low is detected on RDY/DOUT, clock pulses at SCLK clock out the data. Data is shifted out MSB first and is in binary two's complement format. Once all the data has been shifted out, a 25th SCLK is required to pull the RDY/DOUT output back to the idle high state. See Figure 2. If the data is not read before the next conversion data is updated, the old data is lost, as the new data overwrites the old value. Data Read Followed by Self-Calibration To initiate self-calibration at the end of a data read, provide a 26th SCLK pulse. After reading the 16 bits of conversion data, a 25th positive edge on SCLK pulls the RDY/DOUT output back high, indicating end of data read. Provide a 26th SCLK pulse to initiate a self-calibration routine starting on the falling edge of the 26th SCLK. A subsequent falling edge of RDY/DOUT indicates data availability at the end of calibration. The timing is illustrated in Figure 3.
t5 SCLK t3 RDY/DOUT D17 1 2
t1 t2 3 24 t4
D16
0 t6
CONVERSION IS DONE DATA IS AVAILABLE t7
CONVERSION IS DONE DATA IS AVAILABLE
Figure 1. Timing Diagram for Data Read After Conversion
SCLK
1
2
3
24
25 25TH SLK RISING EDGE PULLS RDY/DOUT HIGH
RDY/DOUT D17 CONVERSION IS DONE DATA IS AVAILABLE D16 0
CONVERSION IS DONE DATA IS AVAILABLE
Figure 2. Timing Diagram for Data Read Followed by RDY/DOUT Being Asserted High Using 25th SCLK
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18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface MAX11212
CALIBRATION STARTS ON 26TH SCLK SCLK 1 2 3 24 25 26 1 2
RDY/DOUT D17 CONVERSION IS DONE DATA IS AVAILABLE D16 0
25TH SCLK PULLS RDY/DOUT HIGH D17 CONVERSION IS DONE DATA IS AVAILABLE AFTER CALIBRATION t8 D16
Figure 3. Timing Diagram for Data Read Followed by Two Extra Clock Cycles for Self-Calibration
DEVICE ENTERS SLEEP MODE SCLK 1 2 t9 t10 RDY/DOUT D17 CONVERSION IS DONE DATA IS AVAILABLE D16 0 3 24 SLEEP MODE
DEVICE EXITS OUT SLEEP MODE 1 2
D17 CONVERSION IS DONE DATA IS AVAILABLE t11
D16
Figure 4. Timing Diagram for Data Read Followed by Sleep Mode Activation; Single-Conversion Timing
Data Read Followed by Sleep Mode The MAX11212 can be put into sleep mode to save power between conversions. To activate the sleep mode, idle the SCLK high any time after the RDY/DOUT output goes low (that is, after conversion data is available). It is not required to read out all 18 bits before putting the part in sleep mode. Sleep mode is activated after the SCLK is held high (see Figure 4). The RDY/DOUT output is pulled high once the device enters sleep mode. To come out of sleep mode, pull SCLK low. After the sleep mode is deactivated (when the device wakes up), conversion
starts again and RDY/DOUT goes low, indicating the next conversion data is available. See Figure 4. Single-Conversion Mode For operating the MAX11212 in single-conversion mode, activate and deactivate sleep mode between conversions as described in the Data Read Followed by Sleep Mode section). Single-conversion mode reduces power consumption by shutting down the device when idle between conversions. See Figure 4. Single-Conversion Mode with
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11
18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface MAX11212
Self-Calibration at Wake-Up The MAX11212 can be put in self-calibration mode immediately after wake-up from sleep mode. Selfcalibration at wake-up helps to compensate for temperature or supply changes if the device is shut down for extensive periods. To automatically start self-calibration at the end of sleep mode, all the data bits must be shifted out followed by 25th SCLK edge to pull RDY/DOUT high, and then on the 26th SCLK keep it high for as long as shutdown is desired. Once SCLK is pulled back low, the device automatically performs a self-calibration and, when the data is ready, the RDY/DOUT output goes low. See Figure 5. This also achieves the purpose of single conversions with self-calibration.
25TH SCLK PULLS RDY/DOUT HIGH
DEVICE ENTERS SLEEP MODE 25 26 SLEEP MODE
DEVICE EXITS OUT SLEEP MODE AND STARTS CALIBRATION 1 2
SCLK
1
2
3 t10
24
RDY/DOUT D17 CONVERSION IS DONE DATA IS AVAILABLE D16 0 D17 CONVERSION IS DONE DATA IS AVAILABLE AFTER CALIBRATION t12 D16
Figure 5. Timing Diagram for Sleep Mode Activation Followed by Self-Calibration at Wake-Up
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18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface
Applications Information
See Figure 6 for the RTD temperature measurement circuit and Figure 7 for a resistive bridge measurement circuit. PROCESS: BiCMOS
MAX11212
Chip Information
IREF2
REFP RREF REFN AINP RRTD AINN GND
Package Information
MAX11212
IREF1 IREF1 = K x IREF2
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 10 MAX PACKAGE CODE U10+2 DOCUMENT NO. 21-0061
Figure 6. RTD Temperature Measurement Circuit
AVDD REFP
REFN
AINP
MAX11212
AINN
Figure 7. Resistive Bridge Measurement Circuit
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18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface MAX11212
Revision History
REVISION NUMBER 0 REVISION DATE 4/10 Initial release DESCRIPTION PAGES CHANGED --
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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(c)
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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Price & Availability of MAX11212AEUB

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